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<title> Papers written by members of the Multiscalar Research Group </title>
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<!WA0><!WA0><!WA0><!WA0><IMG SRC="http://www.cs.wisc.edu/~mscalar/multiscalar.gif" ALT="Multiscalar Logo" ALIGN=MIDDLE>
Papers by members of the Multiscalar Research Group
</h1>
<ul>
<li> Return to <!WA1><!WA1><!WA1><!WA1><A HREF="http://www.cs.wisc.edu/~mscalar/">Multiscalar Home Page</A>
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<ul>

<!WA2><!WA2><!WA2><!WA2><A HREF="ftp://ftp.cs.wisc.edu/sohi/mscalar/tr1310.ps.Z">
<cite>
Trace Cache: A Low Latency Approach to High Bandwidth Instruction Fetching
</cite></A>,
Eric Rotenberg, Steve Bennett, and James E. Smith,
Technical Report #1310, Computer Sciences Department,
University of Wisconsin - Madison, April 1996.
<P>

<!WA3><!WA3><!WA3><!WA3><A HREF="ftp://ftp.cs.wisc.edu/sohi/isca96.HBAT.ps.Z">
<cite>
High-Bandwidth Address Translation for Multiple-Issue Processors</i></a>,
</A>
T. M. Austin and G. S. Sohi, to appear in
23rd Annual International Symposium on Computer Architecture, May 1996.
An appendix of
<!WA4><!WA4><!WA4><!WA4><a href="ftp://ftp.cs.wisc.edu/sohi/isca96-results.ps.Z">detailed results</a>
is also available.)<br>
<P>


<!WA5><!WA5><!WA5><!WA5><A HREF="ftp://ftp.cs.wisc.edu/sohi/micro28.zcl.ps.Z">
<cite>
Zero-Cycle Loads: Microarchitecture Support for Reducing Load Latency
</A>
T. M. Austin and G. S. Sohi,
28th Annual International Symposium on Microarchitecture (MICRO-28), 1995.
<P>


<!WA6><!WA6><!WA6><!WA6><A HREF="ftp://ftp.cs.wisc.edu/sohi/super.proc.ps.Z">
<cite>
The Microarchitecture of Superscalar Processors
</A>
</cite>
J. E. Smith and G. S. Sohi,
in Proceedings of the IEEE.
<P>

<!WA7><!WA7><!WA7><!WA7><A HREF="ftp://ftp.cs.wisc.edu/sohi/arb.ps.Z">
<cite>
ARB: A Hardware Mechanism for Dynamic Reordering of Memory References
</cite>
</A>
M. Franklin and G. S. Sohi,
in IEEE Transactions on Computers.
<P>

<!WA8><!WA8><!WA8><!WA8><A HREF="ftp://ftp.cs.wisc.edu/sohi/isca95.multiscalar.ps.Z">
<cite>
Multiscalar Processors,
</cite>
</A>
G. S. Sohi, S. Breach,  and T. N. Vijaykumar,
22th International Symposium on Computer Architecture, 1995.
<P>

<!WA9><!WA9><!WA9><!WA9><A HREF="ftp://ftp.cs.wisc.edu/sohi/isca95.fast.ps.Z">
<cite>
Streamlining Data Cache Access with Fast Address Calculation,
</cite>
</A>
T. M. Austin, D. N. Pnevmatikatos, and G. S. Sohi,
22th International Symposium on Computer Architecture, 1995.

<P>
<!WA10><!WA10><!WA10><!WA10><A HREF="ftp://ftp.cs.wisc.edu/sohi/micro27.ps.Z">
<cite>
The Anatomy of the Register File in a Multiscalar Processor,
</cite>
</A>
S. Breach, T. N. Vijaykumar, and G. S. Sohi,
27th Annual International Symposium on Microarchitecture (MICRO-27), 1994.

<P>
<!WA11><!WA11><!WA11><!WA11><A HREF="ftp://ftp.cs.wisc.edu/sohi/franklin.thesis.ps.Z">
<cite>
The Multiscalar Architecture
</cite>
</A>
Manoj Franklin,
</A>
Ph.D. thesis,  December 1993,
</A>

<P>
<!WA12><!WA12><!WA12><!WA12><A HREF="ftp://ftp.cs.wisc.edu/sohi/micro26.ps.Z">
<cite>
Control Flow Prediction for Dynamic ILP Processors, 
</cite>
</A>
D. Pnevmatikatos, M. Franklin and G. S. Sohi,
26th Annual International Symposium on Microarchitecture (MICRO-26), 1993.

<P>
<!WA13><!WA13><!WA13><!WA13><A HREF="ftp://ftp.cs.wisc.edu/sohi/isca92.esw.ps.Z">
<cite>
The Expandable Split Window Paradigm for Exploiting Fine-Grain Parallelism,
</cite>
</A>
M. Franklin and G. S. Sohi, 19th International Symposium on Computer Architecture, 1992.

<P>
<!WA14><!WA14><!WA14><!WA14><A HREF="ftp://ftp.cs.wisc.edu/sohi/micro25.ps.Z">
<cite>
Register Traffic Analysis for Streamlining Inter-operation Communication
in Fine-Grain Parallel Processors,
</cite>
</A>
M. Franklin and G. S. Sohi, 25th Annual International Symposium on Microarchitecture
(MICRO-25), 1992.

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<address> Last Updated: 20 September 1995 by Guri Sohi </address>
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